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250ksps 12 bit impedance converter network analyzer prelim inary technical data AD5934 rev. pr a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 50khz max excitation output impedance range .1k C 20m ohm, 12-bit re solution system c l ock provided via m c lk pin dsp real and i m aginary ca lculation (fft) 3v power supp ly, programma ble sinewave output frequency r e s o lution 27 bits (<0.1 hz) frequency sweep capability 12-bit samplin g adc adc s a mpling 250ksps, inl 1lsb max serial i 2 c loadi n g temperature r a nge ?40 C 125c 16 ssop applic ati o ns complex impedance measur e m ent impedance spectrometry biomedical and a u tomotive sensors proximity sens ors fft processing general description the AD5934 is a hig h p r ecisio n im p e dan c e con v er t e r sys t em so l u tio n which co m b in es an o n -bo a r d f r eq uen c y g e n e ra t o r wi th a 12-b i t 250 ks p s ad c. the f r eq uen c y g e n e ra to r al lo ws a n ext e r n al co m p lex im p e dan c e t o b e exci t e d wi t h a k n o w n f r e q uen c y . th e r e s p o n s e sig n al f r o m t h e i m p e da n c e is s a m p le d b y t h e on b o a r d ad c and f f t p r o c ess e d b y a n o n b o a r d dsp en gin e . th e ff t alg o r i thm r e t u r n s a real (r) a nd i m a g ina r y (i) d a t a wor d , a l l o w i ng i m p e d a nc e to b e c o n v e n i e n t ly c a l c u l a t e d . the i m p e dan c e ma g n i t ude an d phas e is e a si l y c a lc u l a t e d usin g th e f o llo w i n g e q ua ti o n s: 2 2 i r magnitude + = ( ) r i tan phase 1 ? = t o deter m i n e t h e ac t u al r e al im p e dan c e va l u e z(w), a f r e q u e nc y s w e e p i s ge ne r a l l y p e r f o r me d. t h e i m p e d a n c e c a n b e cal c ul a t ed a t eac h po in t , a n d a f r eq ue n c y v s . m a gn i t ude p l o t ca n be cr ea t e d . the sys t e m al lo ws t h e us er t o pr og ra m a 2 v pk-pk sin u s o i d a l sig n a l as exci t a t i o n t o an ext e r n a l lo ad . o u t p u t ra n g es o f 1 v , 500 mv , and 200 mv c a n als o b e p r og ra mm e d . the sig n al is p r o v ide d on ch i p s usin g dds t e chniq u es. f r e q uen c y r e s o l u t i o n o f 27 b i ts (les s t h a n 0.1h z) can be ac hieved . t o p e r f o r m t h e f r e q uen c y sw e e p , t h e us er m u s t f i rs t p r og ra m th e co n d i ti o n s r e q u i r ed f o r th e sw ee p; s t a r t f r eq ue n c y , d e l t a f r eq ue n c y , s t e p f r eq ue n c y , e t c. a s t a r t c o m m a n d i s th en r e q u i r ed t o be gin th e s w eep . a t e a c h p o in t on the sw e e p t h e , ad c t a k e s 102 4 s a m p les an d c a l c u l a t e s a d i s c re te f o u r i e r t r ans f or m to prov i d e t h e re a l a n d ima g in a r y da t a fo r t h e wa v e fo r m . t h e r e a l and ima g in a r y da t a is a v a i la b l e t o t h e us er t h r o ug h t h e 12c in t e r f ace . t o deter m i n e t h e im p e dan c e o f t h e lo ad a t an y o n e f r e q ue n c y p o in t, z(w), a me as ur emen t sys t em com p r i s e d of a t r a n s im p e d a n c e am plif ier , ga in st a g e , a nd a d c a r e u s e d t o r e co r d da t a . the ga i n st a g e fo r t h e r e sp o n s e s t a g e is 1 or 5. the ad c is a low-n o is e , hig h -sp eed 250 ks ps s a m p ling ad c th a t o p e r a t e s f r o m a 3 v su p p l y . cloc ki n g f o r b o th th e d d s a n d ad c sig n als is p r o v ide d ext e r n al l y via the mc lk r e fer e n c e clo c k, w h ich is p r o v ide d ext e r n a l ly f r o m a cr y s ta l os ci l l a t o r . t h e AD5934 is a v a i l a b l e in a 16 ld s s o p . fi g u r e 1 .
AD5934 preliminary technical data rev. pra | page 2 of 20 table of contents specifications..................................................................................... 3 timing characteristics..................................................................... 5 pin configuration and function descriptions............................. 6 general description ......................................................................... 7 output stage.................................................................................. 7 circuit description....................................................................... 7 sin rom.......................................................................................... 8 response stage.............................................................................. 8 adc operation ............................................................................ 8 dft conversion ........................................................................... 9 register map.................................................................................... 10 control register.......................................................................... 11 control register map................................................................. 11 control register decode ........................................................... 12 reset ............................................................................................. 12 system clock............................................................................... 12 output voltage............................................................................ 12 post gain ..................................................................................... 12 serial bus interface..................................................................... 13 general i2c timing ................................................................... 13 writing/reading to the AD5934 .......................................... 14 write byte/command byte....................................................... 14 block write.................................................................................. 15 read operations......................................................................... 15 p.e.c. ............................................................................................ 16 checksum.................................................................................... 16 outline dimensions ....................................................................... 17 esd caution................................................................................ 17 revision history 12/04revision pra C preliminary version
preliminary technical data AD5934 rev. pra | page 3 of 20 specifications vdd = +3.0 v 10%. tmin to tmax unless otherwise noted. table 1. b version 1 parameter min typ max unit test conditions/comments system specs impedance range .0001 20 m ohm total system accuracy 1 % system ppm tdb ppm/c mclk update rate 16 msps output stage frequency specs output frequency range 0 50khz hz uni-polar sinusoidal signal frequency resoltuion 27 bits <0.1 hz resolution mclk external reference clock; typically 16.667 mhz initial frequency accuracy 0.1 hz o utput excitation accuracy. 0 -50 khz range output voltage specs ac voltage range 2.0 volts pk-pk unipolar voltage on output output voltage error tbd % voltage error on pk-pk output dc bias vdd/2 volts dc bias of ac signal dc bias error tbd % tolerance of dc bias ac voltage range 1.0 volts pk-pk unipolar voltage on output output voltage error tbd % voltage error on pk-pk output dc bias vdd/4 volts dc bias of ac signal dc bias error 1 % tolerance of dc bias ac voltage range 0.4 volts pk-pk unipolar voltage on output output voltage error tbd % voltage error on pk-pk output dc bias vdd/8 volts dc bias of ac signal dc bias error tbd % tolerance of dc bias ac voltage range 0.2 volts pk-pk unipolar voltage on output output voltage error tbd % voltage error on pk-pk output dc bias vdd/16 volts dc bias of ac signal dc bias error tbd % tolerance of dc bias dc output impedance 120 ohm short circuit current 75 ma at 3 volts short circuit current 100 ma at 5 volts ac characteristics signal to noise ratio 60 db total harmonic distortion ?66 db spurious free dynamic range wideband 60 db narrowband 80 db clock feedthrough tbd db
AD5934 preliminary technical data rev. pra | page 4 of 20 b version 1 parameter min typ max unit test conditions/comments system response stage analog input vin input leakage current 1 na to pin vin input capacitance 0.5 pf to pin vin input impedance 100m ohm to pin vin adc accuracy resolution 12 sampling rate 1 msps integral nonlinearity 1 lsb no missing codes differential nonlinearity 1 lsb offset error gain error temperature sensor accuracy 2 c ta = ?40 C 125 degrees resolution 0.03125 c temperature conversion time tbd s logic inputs vih, input high voltage 2.2 vdd = 3v vil, input low voltage 0.8 vdd = 3v input current 1 a input capacitance 3 pf power requirements vdd 3.0 volts idd (normal mode) 15 ma idd (powerdown mode) tbd a 1 temperature ranges are as follows: b ve rsion: ?40c to +125 c, typical at 25c. 2 guaranteed by design and characterization, not production tested.
prelim inary technical data AD5934 r e v. pr a | pa g e 5 of 20 timing characteristics table 2. i 2 c serial in terface parameter limit at t min , t ma x u n i t d e s c r i p t i o n f scl 400 khz max scl clock frequ e ncy t 1 2.5 s min scl cycle time t 2 0 . 6 s m i n t high , scl high ti me t 3 1 . 3 s m i n t low , scl low time t 4 0 . 6 s m i n t hd, sta , start/repeated start condition hold time t 5 1 0 0 n s m i n t su , da t , data setu p time t 6 0 . 9 s m a x t hd, dat , data hold time 0 s m i n t hd, dat , data hold time t 7 0 . 6 s m i n t su , s t a , setup tim e for repeated start t 8 0 . 6 s m i n t su , s t o , stop con d ition setup time t 9 1 . 3 s m i n t bu f , bus free tim e between a sto p and a start co ndition t 10 3 0 0 n s m a x t f , fall time of s d a when transmitting 0 n s m i n t r , rise time of scl and sda wh en receiving (c mos compatible) t 11 3 0 0 n s m a x t f , fall time of s d a when transmitting 0 n s m i n t f , fall time of s d a when receivi n g (cmos compatible) 300 n s m a x t f , fall time of sc l and sda when receiving 20 + 0.1 c b n s m i n t f , fall time of sc l and sda when transmitting c b 400 pf max capacitive load for each bus li ne fi g u r e 2 . i 2 c i n t e r f ac e timing d i agr a m
AD5934 prelim inary technical data r e v. pr a | pa g e 6 of 20 pin conf iguration and fu nction descriptions f i gure 3. pin config ur ation ta ble 3. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 n / c n o c o n n e c t . 4 rfb_pin external feedback resisto r. this is used to set the gain of the input signal of the vin node. 5 vout output ac ex citation signal. programmble fre qunency range 0-50khz. 6 v i n input signal to transim p edance amplifier. extern al feed bac k resi stor wil l contro l gain of transimp ed ance amplifier. 8 mclk master clock for the system. used to provide out p ut ex citation signal an d as sampling of adc. 9 dvdd digital supply voltage. 10 avdd1 analog supply voltage 1. 11 avdd2 analog supply voltage 2. 1 2 d g n d d i g i t a l g r o u n d . 13 agnd1 analog gnd 1. 14 agnd2 analog gnd 2. 2 5 s d a i 2 c data inpu t. 1 6 s c l i 2 c clock inpu t.
prelim inary technical data AD5934 r e v. pr a | pa g e 7 of 20 gene ral description the AD5934 is a hig h p r ecisio n im p e dan c e con v er t e r sys t em s o lut i on w h i c h c o mb i n e s a n o n b o ard f r e q u e nc y ge ne r a tor w i t h a 12-b i t 1m s p s ad c. th e f r eq u e n c y g e n e ra t o r al lo ws a n ext e r n al co m p lex im p e dan c e t o b e exci t e d wi t h a k n o w n f r e q uen c y . th e r e s p o n s e sig n al f r o m t h e i m p e da n c e is s a m p le d b y t h e o n b o a r d ad c and f f t p r o c ess e d b y a n o n b o a r d dsp en g i n e . th e ff t alg o r i t h m r e t u r n s tw o re al ( r ) a nd i m a g inar y (i) da t a w o r d s. the i m p e dan c e ma g n i t ude an d phas e is e a si l y ca lc u l a t e d usin g t h e fol l o w in g e q ua t i o n s: 2 2 i r magnitude + = () r i tan phase 1 ? = t o deter m i n e t h e ac t u al r e al im p e dan c e va l u e z(w), a f r e q u e nc y s w e e p i s ge ne r a l l y p e r f o r me d. t h e i m p e d a n c e c a n b e cal c ul a t ed a t eac h po in t , a n d a f r eq ue n c y v s . m a gn i t ude p l o t ca n be cr ea t e d . fi g u r e 4 . the sys t e m al lo ws t h e us er t o pr og ra m a 2v pk-pk sin u s o i d a l sig n al as exci ta t i o n t o an ext e r n al lo ad . o u t p u t ra n g es o f 1v , 500mv , 200mv ca n als o be p r og ra mmed . the sig n al is p r o v ided on ch ip u s i n g d d s te ch n i qu e s . f r e q u e nc y re s o lut i on of 2 7 bit s (les s tha n 0.1h z) ca n b e ac hie v ed . th e c l o c k f o r th e d d s c a n be g e n e ra t e d f r o m a n e x t e rn al r e f e r e n c e c l oc k , a n in t e rn al r c os cil l a t o r , o r a n in t e r n al p l l. th e pll has a ga in s t a g e o f 520, a nd ty pica l l y ne e d s a r e fer e n c e clo c k o f 32 khz o n t h e mclk pi n . outpu t st age t h e output s t ag e of t h e a d 5 9 3 4 , show n i n f i g u re 5 , prov i d e s a c o nst a n t output f r e q u e nc y or f r e q u e nc y s w e e p f u nc t i o n w h i c h has a p r og ra mma b le o u t p u t vol t a g e o f 2/1/0.5 / 0.2 v . th e f r eq ue n c y s w eep seq u en ce i s p r e - p r ogra m m e d th r o ugh th e i 2 c in t e r f ace . a n i 2 c co m m a n d i s used t o s t a r t t h e e x ci ta ti o n seq u en c e . fi g u r e 5 . circuit description the AD5934 has a f u l l y in t e g r a t ed dir e c t dig i t a l s y n t h e sis ( d d s ) c o re to ge ne r a te re qu i r e d f r e q u e nc i e s . t h e bl o c k re qu i r e s a re fe re nc e cl o c k to prov i d e di g i t a l l y c r e a te d s i ne w a ve s up to 50khz. this is p r o v ide d t h r o u g h a n ext e r n a l refer e n c e clo c k, mclk. this clo c k is in ter n a l ly divide d do w n b y 4 to p r o v ide t h e re f e re nc e cl o c k or f mc l k t o th e d d s. th e in t e rn al ci r c ui tr y o f t h e dds con s ist s o f t h e fol l o w ing ma in s e c t io n s : a n u m e r i ca l c o n t r o ll ed o s c i ll a t o r (n co ), a f r eq u e n c y m o d u l a t o r , s i n ro m, a nd a dig i t a l- to -a na lo g c o n v er ter . num e ric a l c o ntrolled os cill ator an d ph as e mo dul ator the ma i n com p o n e n t o f t h e nc o is a 27- b i t phas e acc u m u l a to r , w h ich as s e m b le s t h e phas e com p o n e n t o f t h e ou t p ut sig n al . fi g u r e 6 . c o n t in uo us time sig n als ha v e a p h as e ra n g e o f 0 t o 2 p i . o u tside t h is ra n g e o f n u m b ers, t h e sin u s o id f u n c t i o n s r e p e a t t h e m s e l v es in a p e r i o d ic m a nner . the dig i t a l im ple m e n t a t i o n is n o dif f er en t. th e acc u m u l a t o r sim p l y s c ales t h e ran g e o f phas e n u m b ers in t o a m u l t i - b i t d i g i t a l w o r d . t h e phas e acc u m u l a t o r in t h e d d s is i m ple m en t e d w i t h 28 b i ts. th er e f o r e , 2p = 2 27 . lik e w i se , t h e d p h a se t e rm i s scal ed in t o th i s ra n g e o f n u m b e r s 0 < d p has e < 2 27 ? 1. m akin g t h es e s u b s t i t u t i ons in t o t h e e q u a t i on a b ove 27 2 mclk f dphase f = wher e 0 < d p has e < 227 ? 1. (n o t e . f mc lk = m c lk/4) the i n p u t t o t h e phas e acc u m u l a t o r (i .e ., t h e phas e s t ep) is s e l e c t ed fr o m t h e fr e q u e n c y r e g i s t e r . n c o s i n h e r e n t l y g e n e r a t e co n t in uo us p h as e sig n als, th us a v o i din g an y o u t p u t d i sco n t i n u i t y w h en sw i t c h i n g b e t w een f r eq uen c i e s .
AD5934 prelim inary technical data r e v. pr a | pa g e 8 of 20 sin rom t o ma k e t h e o u t p u t f r o m t h e nc o us ef u l , i t m u s t b e con v er t e d f r o m phas e infor m a t io n i n t o a s i n u s o i d a l va l u e. sin c e phas e info r m a t io n m a ps dir e c t ly in t o a m pli t ude , t h e sin ro m us es t h e dig i t a l phas e info r m a t io n as a n addr es s t o a lo ok-u p t a b l e , a nd con v er ts t h e phas e i n fo r m a t io n i n t o am pli t ude . a l t h o u g h t h e n c o con t ai n s a 27- b i t phas e acc u m u l a t o r , t h e o u t p ut o f t h e n c o i s tr un ca t e d t o 12 b i t s . u s i n g th e full r e so l u ti o n o f th e phas e acc u m u l a t o r is im p r ac t i c a l a nd un n e ce ss a r y as t h is w o u l d re qu i r e a l o o k - u p t a bl e of 2 27 en t r ies. i t is n e cess a r y o n ly t o ha v e s u f f i cien t phas e r e s o l u t i o n s u ch t h a t t h e er r o rs d u e t o tr un ca t i o n a r e sm alle r th a n th e r e so l u ti o n o f th e 10- b i td a c . this r e q u ir es t h e s i n r o m t o ha v e tw o b i ts o f phas e r e s o l u t i on m o r e t h an t h e 1 0 -b i t d a c. th e d d s i n cl udes a hig h i m p e dan c e c u r r en t s o ur ce 10-b i t d a c. response s t age the dia g ram b e lo w s h o w s t h e i n p u t s t a g e t o p i n tf1. c u r r en t f r om t h e e x te r n a l s e ns or l o a d f l ow s t h rou g h t h e t f 1 pi n a n d in t o a t r an sim p e d an c e am plif ie r w h ich h a s a n e x t e r n a l r e sist o r acr o s s i t s fe e d bac k . th e us er ne e d s t o c h o o s e a p r e c isio n r e sis t o r in t h e fe e d b a ck lo o p s u ch t h a t t h e d y na mic ra ng e o f t h e ad c i s us e d . t h e p o si t i v e n o de o f t h e t r a n sim p e d an ce a m plif ier is b i as e d t o vd d/2. th e o u t p u t o f th e t r a n sim p e d an c e a m p l if ier ca n t h en be ga in e d b y ei t h er 1 o r 5, a n d is f e d dir e c t l y in t o t h e in p u t o f t h e ad c. fi g u r e 7 . adc opera t ion the AD5934 has a n in t e g r a t e d o n bo a r d 12 -b i t ad c. th e ad c co n t a i n s an o n - c hi p t r ack and h o ld am plif ier , a successi ve a p p r o x im a t ion a/d con v er t e r . c l o c k i n g fo r t h e a/ d is p r o v id e d usin g a divid e d do wn r a t i o o f t h e r e fer e nce clo c k. the a / d is a s u cces si v e a p p r o x i m a t ion a n alog to dig i t a l co n v er t e r , bas e d o n a c a p a c i ti ve dac desig n ar chi t ec t u r e . th e f i gur e s be lo w s h o w sim p lif i e d s c h e ma tics o f t h e ad c. th e ad c is co m p r i s e d o f co n t r o l log i c, a sar , an d a c a p a ci ti v e d a c, al l o f w h ich a r e us e d to ad d and sub t r a c t f i xe d am o u n t s o f cha r ge f r om t h e s a m p l i ng c a p a c i tor to b r i n g t h e c o m p ar a t or b a c k i n to a b a lance d cond i t io n. the 1 st f i gur e s h o w s t h e a d c d u r i n g i t s acq u isi t ion pha s e . sw2 is clos e d an d s w 1 is i n p o si t i o n a, t h e co m p a r a t o r is he ld in a ba lan c e d con d i t io n, and the s a m p lin g ca p a c i t o r acq u ires t h e sig n al on v a 1, fo r exa m pl e . fi g u r e 8 . w h en t h e ad c s t a r ts a con v ersio n , sw2 wi l l op en and s w 1 wil l m o v e t o p o si tio n b , as sh o w n b e lo w , ca usin g th e co m p a r a t o r t o b e co me u n bal a nced . th e con t r o l log i c a n d t h e ca p a c i t i ve d a c a r e us e d to ad d a nd sub t r a c t f i x e d am o u n t s o f ch arge f r om t h e s a m p l i ng c a p a c i tor to b r i n g t h e c o m p ar a t or bac k in t o a b a lan c e d con d i t ion. w h en t h e com p a r a t o r is r e - b a lan c e d , t h e con v ersio n is com p let e . th e con t r o l log i c ge ne r a te s t h e a d c output c o de . fi g u r e 9 . the s t a r t con v e r sio n fo r t h e a d c is ei t h er us e r co n t r o l l e d v i a a n ext e r n al adc _ tr ig p i n o r can be in t e r n al l y p r og ra mm e d as a de l a y f r o m t h e st a r t o f t h e exci t a t i o n sig n al . the da t a f r o m t h e ad c is dir e c t l y a v a i la b l e on t h e i 2 c in ter f ace o r ca n e i t h er b e s t o r ed in a fifo ra m un t i l th e e n ti r e f r eq uen c y s w ee p i s co m p let e d .
prelim inary technical data AD5934 r e v. pr a | pa g e 9 of 20 df t co nve r sion a dis c r e t e f o ur ier t r a n sfo r m is ca lc u l a t e d fo r e a ch f r e q uen c y p o in t in t h e sw e e p . the r e t u r n s i g n a l is con v er t e d b y t h e a d c, wi n d o w e d , an d t h e n m u l t i p lie d wi t h a t e st ph as o r va l u e t o g i ve a r e al a nd ima g ina r y o u t p u t . this is r e p e a t e d f o r 1024 s a m p le po i n t s o f th e in p u t si gn al a n d th e r e s u l t s o f ea c h m u l t i p li ca ti o n s u mm e d t o g i v e a f i nal a n s w er as a co m p lex n u m b er . th e r e s u l t a n t a n s w er a t ea c h f r eq uen c y i s t w o 16-b i t w o r d s , th e r e al a nd im a g ina r y d a t a in com p lex fo r m . f i g u re 10. the df t a l go r i t h m is r e p r es en te d b y ( ) ( )( ) ( ) [ ] n jsine n cos n x sum f x ? = b o th the r e al and ima g ina r y da t a r e g i s t er ha v e 1 5 b i ts o f da ta a nd on e sig n b i t . th e 15 b i ts o f da t a a r e in 2 s c o m p lim e n t fo r m a t . the mag n i t ude o f t h e si g n al ca n b e r e p r es en t e d b y 2 2 i r magnitude + = t h i s r e t u r n ed m a gn i t ud e i s a s c al ed v a l u ed o f th e a c t u al co m p lex im p e da n c e m e as ur e d . the m u l t i p lic a t i o n fac t o r b e tw e e n t h e mag n i t ude r e t u r n e d an d t h e ac t u al im p e dan c e is cal l e d t h e g a i n f a ct o r . the us er n e e d s t o t h e n calc u l a t e t h is gain f a ct o r val u e an d us e i t fo r cali b r a t io n in t h e sys t e m .
AD5934 preliminary technical data rev. pra | page 10 of 20 register map the register map contains the registers where the frequency sweep data is loaded, and the resultant real and imaginary data is stored. each row equals 8 bits of data. table 4. register map register name reg add. register data [8 bits] read/write register register type ram control register 80h d15 - d8 read/write ram 81h d7 - d0 read/write ram start frequency (24 bits) 82h d23 - d16 read/write ram 83h d1 5 -d8 read/write ram 84h d7 - d0 read/write ram frequency increment word 85h d23 - d16 read/write ram 86h d15 - d8 read/write ram 87h d7 -d0 read/write ram no of increments (9 bits) 88h d15 - d8 read/write ram bits d15-d9 = dont care bits d8-d0 = number of frequency increments settling time cycles (16 bits) 8ah d15 - d8 read/write ram d15 C d11= dont care d10 C d9 = 2 bit decode d8 C d0 = number of cycles d10 d9 0 0 default 0 1 number of cycles 2 1 0 reserved 1 1 number of cycles 4 8bh d7 - d0 read/write ram leakage limit for test a 8ch d7 - d0 read/write ram d7 C d4 = dont care d3 C d0 = 4-bit limit leakage limit for test b 8dh d7 - d0 read/write ram d7 C d4 = dont care d3 C d0 = 4 bit-limit leakage limit for test c 8eh d7 - d0 read/write ram d7 C d4 = dont care d3 C d0 = 4 bit-limit status register 8fh d7 - d0 read/write ram index counter of frequency (9 bits) 90h d15 - d8 read only ram bits d15 C d9 = dont care bits d8 C d0 = increments register after a frequency increment command. set to zero at initial frequency. 91h d7 - d0 read only temperature data 92h d15 - d8 read only ram register 93h d7 - d0 read only ram real data 94h d15 - d8 read only ram 95h d7 - d0 read only ram imaginary data 96h d15 - d8 read only ram 97h d7 - d0 read only ram checksum 98h d7-d0 read only ram
preliminary technical data AD5934 rev. pra | page 11 of 20 control register the AD5934 contains a 16-bit control register that set the AD5934 control modes. the five msbs of the control register are deco ded to provide control functions for frequency sweep, power down and various other control functions, defined in table below. the othe r command functions of the control register are explained on the following pages. note: for error checking on the control register it is advised to write one byte at a time with pec enabled. this allows full e rror checking to be completed before the control register is updated and therefore ensures the control is not updated with incorrect data. th e control register will power-up in the following state xa000h (i.e. in powerdown) control register map table 5. control register map bit d15 d15 d14 d13 d12 d11 frequency sweep d14 0 0 0 0 0 no operation/ exit fuse blow mode d13 0 0 0 0 1 initialize sensor with start frequency d12 0 0 0 1 0 start frequency sweep d11 0 0 0 1 1 increment frequency 0 0 1 0 0 repeat frequency 0 1 0 0 0 reserved 0 1 0 0 1 reserved 0 1 0 1 0 power down 0 1 0 1 1 standby mode d10 external calibration mode = 1 d9 d9 d8 output voltage d8 0 0 no divide. (normal mode = 2.0v) 0 1 divide by 10 (200mv) 1 0 divide by 5 (400mv) 1 1 divide by 2 (1.0v) d7 post gain 0 = multiply x 5; 1 = multiply x 1. d6 error checking enable = 1; disable=0 d5 reserved. set to 0 d4 reset d3 0 reserved d2 0 reserved d1 0 reserved d0 0 reserved
AD5934 preliminary technical data rev. pra | page 12 of 20 control register decode initialize sensor with start frequency this command enables the dds to output the start frequency for an indefinite time. it is used is to excite the sensor initially. when the output load (sensor) has settled after a time determined by the user, the user must initiate a start frequency sweep command to begin the frequency sweep start frequency sweep this command starts the frequency sweep routine. when the ad11/2043 receives this command, it starts counting a delay cycle that will gate the adc conversion pulse. this delay cycle has already been pre-programmed as number of output cycles by the user. increment frequency the increment frequency command is used to step to the next frequency point in the sweep. this usually happens after data from the previous step has been transferred and verified by the dsp. repeat frequency repeat frequency allows the user to repeat any given frequency if the data gets corrupted or the measurement sequence does not complete. power down power down powers down all the blocks in the chip except the interface. all amplifiers and the oscillator will be powered off. the default on power-up of the ad11/2043 is powerdown and the control register will contain the code 1010000000000000. in this mode both the output and input pins dds_out and in_adc will be tied to gnd. standby mode powers the part up for general operation; all the amplifiers will be powered up but their outputs will be tied to gnd. the internal oscillator will also be powered up and running. read temperature this initiates a temperature reading from the part. the part does not need to be in power up mode to perform a temperature reading. the block will power itself up, take the reading and then power down again. error checking set bit in control register to enable this. enable = 1; disable=0 reset a reset will refresh all memory, reset adc, frequency reverts to the initial start frequency system clock allows the user to configure either the internal oscillator or an external reference clock, or allows an internal pll to provide a clock for the system. in pll mode the user will have to provide a stable ~32khz clock as reference to the pll. output voltage this allows the user to change the excitation voltage levels. there are for output ranges, 2v, 1v, 500mv, 200mv. post gain allows the user to multiply pre-amp the response signal by a multiplication factor of 5 into the adc, if required.
prelim inary technical data AD5934 r e v. pr a | pa g e 13 o f 20 f i gure 11. p e r f or mi ng a f r equ e nc y s w eep C f l o w cha r t serial bus interface c o n t r o l o f th e AD5934 is ca r r i ed o u t via t h e 1 2 c s e r i al i n t e r f ace p r o t o c ol . th e AD5934 is co nnec t e d t o this b u s as a s l a v e de vi ce , under t h e con t r o l o f a mas t er de vi ce . the AD5934 has a 7-b i t s e r i al b u s s l a v e addr es s. w h en t h e de vice is p o w e r e d u p , i t w i l l do s o wi t h a d e fa u l t s e r i a l b u s addr es s; 000110 1. general i 2 c timing the dia g ram b e lo w s h o w s t h e t i min g di a g ra m fo r g e n e ral r e ad a nd wr i t e op era t io n s usin g t h e i 2 c in ter f ace . the g e n e ral i 2 c p r o t o c ol op e r a t e s a s f o l l o w s : f i g u re 12. ? the mas t er ini t i a t e s da t a t r an sfer b y es t a b l is hing a st a r t co ndi t i on, def i ne d as a hig h to lo w t r a n si t i o n on t h e s e r i a l da ta lin e s d a w h ile th e se ri al c l oc k lin e scl r e m a i n s hi gh . t h i s in di ca t e s t h a t a da t a s t r e a m w i ll f o llo w . t h e sla v e r e sp o n d s t o t h e st ar t con d i t ion an d shif t in t h e n e xt 8 b i ts, co n s is ting o f a 7-b i t sla v e addr es s (ms b f i rs t) p l us a n r/w b i t, w h ich deter m i n es t h e dir e c t io n o f t h e d a t a t r ans f e r , i. e. w h e t he r da t a w i l l b e w r i tte n to or re a d f r om t h e sla v e de v i ce (0 = wr i t e , 1 = r e ad).
AD5934 preliminary technical data rev. pra | page 14 of 20 ? the slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is a 0, then the master will write to the slave device. if the r/w bit is a 1, the master will read from the slave device. ? data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. since data can flow in only one direction as defined by the r/w bit, it is not possible to send a command to a slave device during a read operation. before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. ? when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10 th clock pulse to assert a stop condition. in read mode, the master device will release the sda line during the low period before the 9 th clock pulse, but the slave device will not pull it low. this is known as no acknowledge. the master will then take the data line low during the low period before the 10th clock pulse, then high during the 10 th clock pulse to assert a stop condition. writing/reading to the AD5934 the interface specification defines several different protocols for different types of read and write operations. those used in the AD5934 are discussed below. these abbreviations are used: s - start p - stop r - read w - write a - acknowledge a - no acknowledge write byte/command byte in this operation, the master device sends a byte of data to the slave device. the write byte can either be a data byte write to a ram location or can be a command operation. to write data to a register the command sequence is as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a register address. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. table 6. writing register data to register address s slave address w a register address a register map a p in the AD5934, the write byte protocol is also used to set a pointer to a register location. this is used for a subsequent single byte read from the same address or block read or write starting at that address. this is done as follows: to set a register pointer the following sequence is applied: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code (pointer command 1011 0000). 5. the slave asserts ack on sda. 6. the master sends a data byte (register location pointer is to point to). 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction.
preliminary technical data AD5934 rev. pra | page 15 of 20 table 7. setting pointer to register address s slave address w a pointer command 011 0000 a register location to point to a p block write in this operation, the master device writes a block of data to a slave device. the start address for a block write must previously have been set. in the case of the AD5934 this is done by setting a pointer to set the ram/otp address. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends an 8-bit command code (10100000) that tells the slave device to expect a block write. 5. the slave asserts ack on sda. 6. the master sends a data byte that tells the slave device the number of data bytes will be sent to it. 7. the slave asserts ack on sda. 8. the master sends the data bytes. 9. the slave asserts ack on sda after each data byte. 10. the master asserts a stop condition on sda to end the transaction table 8. writing a block write s slave address w a block write a number bytes write a abyte0 a byte1 a byte2 a p read operations the AD5934 uses the following i 2 c read protocols: receive byte in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no ack on sda. (slave needs to check that master has received data) 6. the master asserts a stop condition on sda and the transaction ends. in the AD5934, the receive byte protocol is used to read a single byte of data from a ram or otp memory location whose address has previously been setting the address pointer. table 9. reading register data s slave address r a register data a p block read in this operation, the master device reads a block of data from a slave device. the start address for a block read must previously have been set. this is again done by setting a pointer to set the ram/otp address. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code (10100001) that tells the slave device to expect a block read. 5. the slave asserts ack on sda. 6. the master sends a byte count data byte that tells the slave how many data bytes to expect. 7. the master asserts ack on sda. 8. the master asserts a repeat start condition on sda. (this is required to set read bit high) 9. the master sends the 7-bit slave address followed by the read bit (high). 10. the slave asserts ack on sda. 11. the master receives the data bytes. 12. the master asserts ack on sda after each data byte. 13. a nack is generated after the last byte to signal the end of the read. 14. the master asserts a stop condition on sda to end the transaction.
AD5934 prelim inary technical data r e v. pr a | pa g e 16 o f 20 table 10. s sla v e ad d r es s w a b l o c k r e ad a numbe r bytes r e ad a s table 11. sla v e ad d r es s r a b y t e 0 a byte 1 a b y t e 2 a p performing a block r e ad error corr ecti on p.e.c. the AD5934 p r o v ides the o p tion o f is s u in g a pec (p ac k e t er r o r c o r r e c t i o n ) b y t e a f t e r al l co mma n ds. this enab les t h e us er t o v e r i f y tha t th e da ta r e c e i v e d b y o r s e n t f r o m t h e AD5934 is co r r ec t. th e p e c b y t e is an o p tio n al b y t e s e n t a f t e r tha t l a s t da t a b y te h a s b e e n w r i t te n to or re a d f r om t h e a d 5 9 3 4 . the proto c o l is as fol l o w s:C 1. the AD5934 is sues a p e c b y t e to th e mas t er . the mas t er sh o u ld che c k t h e pec b y t e and issue an o t h e r b l o c k r e ad if t h e pe c b y t e is in co r r e c t. 2. a n a c k i s ge ne r a te d af te r t h e pe c b y te to s i g n a l t h e e nd of t h e re a d . 3. the pec is ge nera t e d p e r t h e fol l o w in g sp e c if i c a t ion s . n o te : th e pe c b y te i s c a l c u l a t e d u s i n g c r c - 8 . th e f r a m e ch eck s e q u en ce (fc s ) co n f o r m s t o c r c- 8 b y th e po l y n o m i al: () 1 1 2 8 + + + = checksum a che c ks u m r e g i s t er is a v ai lab l e t o al lo w t h e us er t o v e r i f y t h e co rr ect co n t e n t s o f th e f r eq ue n c y r e gi s t e r , f r eq u e n c y in cr em e n t r e g i s t er , a nd n u m b er o f in cr emen ts. th e che c ks um r e g i s t er is b a s e d on a n e r ror che c k i ng a l g o r i t h m f r om t h e ab ove re g i st e r s . tbd . the us er r e ads t h is ch e c ksum r e g i s t er and v e r i f i es co n t en ts a r e co r r ec t. u s er c o mm an d c o d e s th e s e co mmand co des a r e us e d fo r r e adin g/ w r i t in g t o t h e in t e r f ace a nd t h e m e m o r y . th e y a r e f u r t h e r expla i ne d in t h e a ppropr i a t e s e c t i o ns but are g r oup e d he re f o r e a s e of re f e re nc e. table 12. command code code na m e c o d e des c ri pt i o n . 1010 0000 bloc k write this command i s used when wri t ing multiple bytes to the ram. see block write section for further explana t ions. 1010 0001 bloc k read this command i s used when rea d ing multiple bytes from the ram / m e mory. see bloc k write section for further expl anation s . 1011 0000 addres s pointer this command enables the user to set the address pointer to any locat i on in the memory. the data will contain the address register of the register the pointer sh ould be pointing to.
prelim inary technical data AD5934 r e v. pr a | pa g e 17 o f 20 outline dimensions f i gure 13. 1 6 -l ead shrink sm al l o u t lin e p a ckage [s sop ] ( r s-16) esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD5934 preliminary technical data rev. pra | page 18 of 20 notes
preliminary technical data AD5934 rev. pra | page 19 of 20 notes
AD5934 prelim inary technical data r e v. pr a | pa g e 20 o f 20 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . pr05325-0-12/04(pr a)

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